The present invention relates generally to integrated circuits, and more specifically the invention pertains to a high speed logic device designed to increase the speed of the logic circuitry.
Modern information processing systems use high speed counters, programmable dividers, feedback shift registers (such as pseudo-noise code generators), and other circuits requiring high speed logic. Some of the types of systems requiring these functions include high performance frequency synthesizers, frequency-agile and/or low-probability-of-intercept radars, and spread-spectrum communications. All of these devices make use of semiconductor transistor circuits which have performance characteristics that are inherently limited by their switching lines.
The task of increasing the logic circuit speed for high speed logic devices is alleviated, to some extent, by the systems disclosed in the following U.S. Patents, the disclosures of which are incorporated herein by reference:
U.S. Pat. No. 4,400,632 issued to Kushner;
U.S. Pat. No. 4,521,700 issued to Blumberg; and
U.S. Pat. No. 4,609,837 issued to Yagyuu.
The patent of Kushner teaches the use of a differential transistor with feedback to increase circuit speed. The patent of Blumberg teaches a passive feedback circuit to increase logic speed. The patent of Yagyuu teaches a high speed logic circuit formed of a differential transistor circuit and a feedback circuit.
The present invention effectively increases the output voltage of the driving gate during a transition for a time of the order of the propagation delay of a gate; in the frequency domain, this is more or less equivalent to peaking the high frequency gain of the gate.
Previous circuit design techniques to peak the high frequency gain in monolithic integrated circuits have utilized the inductive component of a transistor emitter impedance as part of the collector load impedance, but this type of circuit requires higher power supply voltage (by one diode forward voltage) for an equivalent logic complexity, or alternatively, reduced the logic circuit complexity that can be achieved with a given power supply voltage. This use of emitter inductance for peaking does not allow as much latitude in choice of the peaking characteristic, and is more noisy than the new circuit described here. The use of actual inductors in the form of a flat spiral of conductor on the integrated circuit has been used in some GaAs linear integrated circuits, but is not generally considered practical in logic circuits.
While the prior art methods are instructive, the need to enhance the performance characteristics of high speed circuits is an ongoing technical concern. The present invention is intended to help satisfy that need.